Not all of the predefined macros shown here are available [Predefined macros are used more extensively than in earlier The predefined macros in the following makefile are listed below. Predefined macros are also used extensively within make's implicit rules.

Macros also provide access to the CFLAGS macro (and other FLAGS macros) for supplying compiler options from the command line. Using predefined macros eliminates the need to edit makefiles when the underlying compilation environment changes. The next example performs exactly the same function, but demonstrates the use of make's predefined macros for the indicated compilation commands. In this example, make produces the object files main.o and data.o, and the executable file functions: $ makeĬc -O -c data.c Using make's Predefined Macros Table 4-4 Simple Makefile for Compiling C Sources: Everything Explicit # Simple makefile for compiling a program from The following makefile is not elegant, but it does the job.

This method requires more disk space, but subsequent (repetitive) recompilations need to be performed only on those object files for which the sources have changed, which saves time. o) file, and then by linking the object files to form an executable ( a.out) file.

Many include library routines, either from one of the standard system libraries or from a user-supplied library.Īlthough it might be easier to recompile and link a single-source program using a single cc command, it is usually more convenient to compile programs with multiple sources in stages-first, by compiling each source file into a separate object (. Most C programs, however, are compiled from several source files. In previous examples you have seen how to compile a simple C program from a single source file, using both explicit target entries and implicit rules.

How to make makefile for c program